The present invention relates to semiconductor integrated circuits, and in particular, to a semiconductor integrated circuit that incorporates a phase-locked loop (PLL) circuit and a plurality of clock and data recovery (CDR) circuits for synchronization of clocks used in a plurality of serial transmission channels.
In the network field, a transmission technology based on serial transmission has been developed. Currently, serial transmission in the network field mainly uses a technique of embedding clock information (encoded data) in a series of data, transmitting the data at the transmitting side and decoding a clock from the transmitted data at the receiving side for synchronization between transceivers.
Network devices usually include PLL circuits and CDR circuits in order to synchronize clocks between remote places connected over a network.
FIG. 7 is a block diagram of a known conventional PLL circuit. A PLL circuit 70 includes a phase-frequency detector (PFD) 71, a charge pump (CP) 72, a loop filter (LF) 73, a voltage-to-current converter (V-I) 74, an oscillator (OSC) 75, and a frequency divider (DIV) 76. When a reference clock REFCLK is externally input to the PLL circuit 70, the phase frequency detector 71 compares the reference clock REFCLK to a divided signal DIVCLK into which the frequency of an oscillation output signal GCLK from the oscillator 75 is divided to detect the phase and frequency differences therebetween. The phase frequency detector 71 outputs an up pulse signal UP or a down pulse signal DOWN to the charge pump 72, depending on the phase difference and frequency difference. The charge pump 72 charges or discharges the loop filter 73 on the basis of the up pulse signal UP or the down pulse signal DOWN. A control voltage VTUNE determined by an electric charge stored in a capacitance of the loop filter 73 is converted into a frequency control current ICTRL in the voltage-to-current converter 74. The frequency control current ICTRL is used to control an oscillation frequency of the oscillator 75.
In this way, the phase difference and the frequency difference between the reference clock REFCLK and the oscillation output signal GCLK from the oscillator 75 are detected, and in accordance with the detected values, the oscillation frequency of the oscillator 75 is repeatedly changed, so that the phase and frequency of the reference clock REFCLK and the phase and frequency of the oscillation output signal GCLK are synchronized with each other.
FIG. 8 is a block diagram of a conventional serial-to-parallel converter (S/P) for converting serial data into parallel data by using a CDR circuit. As shown in FIG. 8, a serial-to-parallel converter 80 includes a deserializer 84 and a CDR circuit 81 having a phase detector (PD) 82 and a phase control block 83. The phase detector 82 detects the leading edge and the trailing edge of serial data signals RXP and RXN (which are differential data), and transmits to the phase control block 83 phase differences between the serial data signals RXP and RXN and clocks GCLKI, GCLKQ, GCLKIB, and GCLKQB. The clocks GCLKI, GCLKQ, GCLKIB, and GCLKQB are generated by a PLL circuit and 90 are degrees out of phase with the adjacent clock. The phase control block 83 shifts the phases of the clocks GCLKI, GCLKQ, GCLKIB, and GCLKQB such that the phases of these clocks are synchronized with the phases of the serial data signals RXP and RXN. Clocks FCLKI and FCLKIB, whose phases have been adjusted by the phase control block 83, are transmitted to the deserializer 84. The deserializer 84 converts the serial data into parallel data in synchronism with the clocks transmitted from the phase control block 83.
FIG. 9 is a block diagram of another conventional serial-to-parallel converter (S/P). A serial-to-parallel converter 90 includes, instead of the phase control block 83 shown in FIG. 8, a coarse loop 92, which is similar to a PLL circuit, and a fine loop 91 for performing control from a phase detector, and a deserializer 93. The coarse loop 92 operates in the same manner as the PLL circuit described above, i.e., compares a low-frequency reference clock REFCLK and a divided signal DIVCLK into which the frequency of an oscillation output signal generated in an oscillator 915 is divided to detect a phase difference therebetween and controls an oscillation frequency of the oscillator 915. If the frequency of the reference clock REFCLK is equal to the frequency of serial data signals RXP and RXN, the fine loop 91 performs an adjustment such that the phases of high-speed clocks GCLKI, GCLKQ, GCLKIB, and GCLKQB which are generated in the oscillator 915, are coincident with the phases of the serial data signals. The high-speed clocks GCLKI and GCLKIB, whose phases have been adjusted in the fine loop 91, are transmitted to the deserializer 93. The deserializer 93 then converts the serial data into parallel data in synchronism with the high-speed clocks GCLKI and GCLKIB from the fine loop 91.
With increases in the amount of traffic on networks in recent years, a technique of binding a plurality of serial transmission channels is used. In this case, it is necessary to perform data communications while the frequencies of clocks in the plurality of serial transmission channels are coincident with each other. The technique is broadly classified into two methods described below.
A first method is a method of supplying a clock from a single PLL circuit to each of the plurality of channels. FIG. 10 is a schematic diagram illustrating this method. Serial-to-parallel converters 80 in FIG. 10 are similar to the serial-to-parallel converter 80 shown in FIG. 8. This method has the advantage of being capable of entirely synchronizing the frequencies of clocks in the channels.
However, as the line becomes finer in semiconductor process technology, line widths and spaces between lines are reduced, and therefore, line resistance and capacitance between lines tend to increase. As a result, as the clock frequency increases its speed from several gigabytes to several tens of gigabytes, deterioration of signal quality, such as a decrease in clock amplitude, an occurrence of jitter, and the like, tends to occur in channels that are remote from each other in layout. To address this problem, a buffer inserted into a path of clock wiring or a shielding of wire is required. This imposes limitations on layout of clock wiring on a semiconductor chip.
A second method is a method of arranging a serial-to-parallel converter such as the one shown in FIG. 9 in each channel, and providing commonality among reference clocks of the serial-to-parallel converters. FIG. 11 is a schematic diagram illustrating this method. This second method can reduce clock deterioration dependent on the position on layout more than the first method because high-speed clocks are generated in each channel.
However, since a reference clock is shared in the second method, the influence of driven load capacitance is not avoided. Therefore, limitations on layout of clock wiring are still present, although not as much as in the high-speed clock described above. Additionally, both the layout area and power consumption are increased because a coarse loop and a fine loop are disposed in each channel. Moreover, since each coarse loop uses a low-frequency reference clock for synchronization, it is necessary to increase a frequency gain of an oscillator, which results in the occurrence of jitter.
As the second method, various techniques are discussed. For example, Japanese Unexamined Patent Application Publication No. 2000-243939 discloses a technique that allows layout of wiring for a reference clock merely by embedding a reference-clock transmission block in each channel and arranging the channels in a different sequence.
Japanese Unexamined Patent Application Publication No. 2004-015032 discloses a technique that suppresses noise within a chip by arranging a line for a reference clock in a dedicated area on an outermost section of the chip and also reduces the length of the line for the reference clock.
Japanese Unexamined Patent Application Publication No. 11-205133 discloses a technique that reduces variations in the frequency of an oscillator by providing a PLL circuit in a receiver with two loops, one loop functioning to compare a reference clock and a feedback clock and the other functioning to compare serial data and the feedback clock, switching between the two loops at start-up and at which data synchronization is performed, and suppressing a current in a tuning-current generating circuit in an oscillator when synchronization with serial data is performed.
The techniques described in Japanese Unexamined Patent Application Publication Nos. 2000-243939 and 2004-015032 can reduce limitations on layout and suppress the influence of noise caused by a circuit adjacent to a clock line, but do not solve a problem of the increase in the layout area and power consumption because a clock itself is supplied to each channel. Additionally, the problem of the occurrence of jitter remains unsolved because it is necessary to increase the gain of a voltage-controlled oscillator.
The technique described in Japanese Unexamined Patent Application Publication No. 11-205133 suppresses variations in the frequency of the oscillator and thus reduces the occurrence of jitter by not using a reference clock and reducing a tuning current when synchronization with serial data is performed. However, in a state where no serial data is input over a fixed period of time, the first loop for the reference clock is temporarily switched on and, upon receipt of serial data, the second loop is switched on again. Therefore, it is necessary to use a reference clock whose jitter is low. As a result, the problem of the limitations on layout of wiring for the reference clock, and the increase in power consumption caused by a buffer arranged in a path of distribution of the reference clock remains unsolved.